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. Ed(S): Reis, Ricardo; Lubaszewski, Marcelo; Jess, Jochen A.g. - Design of Systems on a Chip: Design and Test - 9781441940896 - V9781441940896
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Design of Systems on a Chip: Design and Test

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Description for Design of Systems on a Chip: Design and Test Paperback. Editor(s): Reis, Ricardo; Lubaszewski, Marcelo; Jess, Jochen A.G. Num Pages: 244 pages, biography. BIC Classification: TBD; TJFC. Category: (P) Professional & Vocational. Dimension: 234 x 156 x 13. Weight in Grams: 348.

Design of Systems on a Chip: Design&Test is the second of two volumes addressing the design challenges associated with new generations of the semiconductor technology. The various chapters are the compilations of tutorials presented at workshops in the recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip. In particular this second book include contributions on three different, but complementary axes: core design, computer-aided design tools and test methods. A collection of chapters deal ... Read more

Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. A large set of methods for designing fault tolerance systems in SRAM-based FPGAs is described. Some presented techniques are based on developing a new fault-tolerant architecture with new robustness FPGA elements. Other techniques are based on protecting the high-level hardware description before the synthesis in the FPGA. The reader has the flexibility of choosing the most suitable fault-tolerance technique for its project and to compare a set of fault toleranttechniques for programmable logic applications.

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Product Details

Format
Paperback
Publication date
2010
Publisher
Springer-Verlag New York Inc. United States
Number of pages
244
Condition
New
Number of Pages
234
Place of Publication
New York, NY, United States
ISBN
9781441940896
SKU
V9781441940896
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15

About . Ed(S): Reis, Ricardo; Lubaszewski, Marcelo; Jess, Jochen A.g.
Ricardo Reis is a former president of the Brazilian Computer Society and former vice-president of the Brazilian Microelectronics Society. He is now trustee of both societies. He is a trustee and former vice-president of the International Federation for Information Processing, IFIP. He received the Silver Core Award from IFIP. He is member of IFIP TC10 and WG 10.5. He is ... Read more

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