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Verification by Error Modeling
Radecka, Katarzyna; Zilic, Zeljko
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Description for Verification by Error Modeling
Paperback. Series: Frontiers in Electronic Testing. Num Pages: 231 pages, biography. BIC Classification: TJFC; UGC; UM. Category: (P) Professional & Vocational. Dimension: 235 x 155 x 12. Weight in Grams: 367.
1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be “imminently doable” by Intel fellow J. Crawford at Microprocessor Forum in October 2002 [40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering ... Read more
1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be “imminently doable” by Intel fellow J. Crawford at Microprocessor Forum in October 2002 [40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering ... Read more
Product Details
Format
Paperback
Publication date
2010
Publisher
Springer-Verlag New York Inc. United States
Number of pages
231
Condition
New
Series
Frontiers in Electronic Testing
Number of Pages
216
Place of Publication
New York, NY, United States
ISBN
9781441954022
SKU
V9781441954022
Shipping Time
Usually ships in 15 to 20 working days
Ref
99-15
Reviews for Verification by Error Modeling
From the reviews: "This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. … The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)